54F377 flip-flop equivalent, octal d flip-flop.
Y Ideal for addressable register applications Y Clock enable for address and data synchronization
applications Y Eight edge-triggered D flip-flops Y Buffered common clock.
Y Clock enable for address and data synchronization
applications Y Eight edge-triggered D flip-flops Y Buffered common c.
The ’F377 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs The common buffered Clock (CP) input loads all flip-flops simultaneously when the Clock Enable (CE) is LOW
The register is fully edge-triggered The state of e.
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